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1 of 64 GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 GS1572 multi-rate serializer with cable driver and clockcleaner tm www.gennum.com key features ? hd-sdi, sd-sdi, dvb-asi transmitter ? integrated smpte 292m and 259m-c compliant cable driver ?integrated clockcleaner ? ? user selectable video processing features, including: ? generic ancillary data insertion ? support for hvf or eia/cea-861 timing input ? automatic standard detection and indication ? enhanced smpte 352m payload id entifier generation and insertion ? trs, crc, anc data chec ksum, and line number calculation and insertion ? edh packet generation and insertion ? illegal code remapping ? smpte 292m and smpt e 259m-c compliant scrambling and nrz nrzi encoding ? blanking of input hanc and vanc space ? jtag test interface ? 1.8v core and 3.3v charge pump power supply ? 1.8v and 3.3v digital i/o support ? low power standby mode ? operating temperature range: -20 o c to +85 o c ? pb-free, rohs compliant, 11mm x 11mm 100-ball bga package applications ? smpte 292m and smpte 259m-c serial digital interfaces ? dvb-asi serial digital interfaces description the GS1572 is the next gene ration multi-standard serializer with an integrated cable driver. the device provides robust parallel to serial conversion, generating a smpte 292m/259m-c compliant serial digital output signal. the integrated cable driver features an output disable (high-impedance) mode and an adjustable signal swing. data input is accepted in 20-bit parallel format or 10-bit parallel format. an asso ciated parallel clock input must be provided at the appropriate operating frequency - 74.25/74.1758/13.5mhz (20-bit mode) or 148.5/148.352/27mhz (10-bit mode). the GS1572 features an internal pll which, if desired, can be configured for a loop ba ndwidth below 100khz. when used in conjunctio n with the go1555 voltage controlled oscillator, the GS1572 can tolera te well in exce ss of 300ps jitter on the input pclk and still provide output jitter within smpte specifications. in addition to serializing the input, the GS1572 performs nrz-to-nrzi encoding and scrambling as per smpte 292m/259m-c when operatin g in smpte mode. when operating in dvb-asi mode, th e device will insert k28.5 sync characters and 8b/10b encode the data prior to serialization. the device also provides a range of other data processing functions. all proc essing features are optional and may be enabled/disabled via external control pin(s) and/or host interface programming. typical power consumption, including the go1555 vco, is 440mw. the standby feature allows the power to be reduced to 125mw. power may be reduced to less than 10mw by also removing the power to the cable driver and eliminating transitions at the parallel data and clock inputs. the GS1572 is pb-free and rohs compliant.
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 2 of 64 functional block diagram GS1572 functional block diagram input mux/ demux din[19:0] smpte 352m generation and insertion anc data insertion trs, line number and crc insertion edh packet insertion nrz/nrzi smpte scrambler dvb asi endec f/de v/vsync h/hsync tim_861 parallel to serial converter mux smpte cable driver sdo sdo rset sdo_en/dis pclk gspi host interface hanc/ vanc blanking phasedetector/ chargepump cp_res vc o 2.5v regulator vc o_vcc vc o_g nd locked cs_tms sclk_tclk sdin_tdi sdout_tdo dvb_as i clockcleaner? lf
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 3 of 64 revision history version ecr pcn date changes and/or modifications 4 151052 52184 march 2009 updated document format. changed figure 4-14: gspi write mode timing . changed parallel input data hold time from 2ns to 0.8ns in table 2-4: ac electrical characteristics . 3 148226 C november 2007 converted from preliminary data sheet to data sheet. updates to; 2.1 absolute maximum ratings , 4.12 gspi host interface , table 4-4: host interface description for raster structure registers , 2.3 dc electrical characteristics , 4.8.4.4 ancillary data checksum generation and insertion , table 2-4: ac electrical characteristics and 4.8.4.1 smpte 352m payload identifier packet insertion . 2 146447 C july 2007 updated typical application circuit . 1 146292 C july 2007 format change. 0 145654 C july 2007 converted from advance information note to preliminary data sheet. changes were made in the following areas: pin descriptions on page 8 , absolute maximum ratings on page 16 , recommended operating conditions on page 17 , dc electrical characteristics on page 17 , ac electrical characteristics on page 18 , smpte mode on page 26 , hvf timing on page 26 , standby mode on page 33 , on page 34 , vanc insertion on page 36 , smpte 352m payload identifier packet insertion on page 40 , edh generation and insertion on page 42 , loop filter on page 45 , lock detect output on page 46 , command word description on page 48 , device reset on page 58 , typical application circuit on page 59 , package dimensions on page 61 , solder reflow profiles on page 62 , packaging data on page 63 , ordering information on page 63 . a 144897 C april 2007 new document.
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 4 of 64 contents key features ................................................................................................................... .....................................1 applications................................................................................................................... ......................................1 description.................................................................................................................... .......................................1 functional block diagram ..................................... .................................................................. .......................2 revision history ............................................................................................................... ..................................3 1. pin out..................................................................................................................... ..........................................7 1.1 pin assignment ............................................................................................................ ......................7 1.2 pin descriptions .......................................................................................................... ......................8 2. electrical characteristics .................................................................................................. ....................... 16 2.1 absolute maximum ratings .................................................................................................. ..... 16 2.2 recommended operating conditions ..... ........... .......... ........... ........... ........... ........... ......... ..... 17 2.3 dc electrical characteristics ...... ....................................................................................... ........ 17 2.4 ac electrical characterist ics ............................................................................................. ........ 18 3. input/output circuits ....................................................................................................... ........................ 20 4. detailed description........................................................................................................ .......................... 23 4.1 functional overview ....................................................................................................... ............. 23 4.2 parallel data inputs ...................................................................................................... ................. 23 4.2.1 parallel input in smpte mode....................................................................................... 24 4.2.2 parallel input in dvb-asi mode................................................................................... 24 4.2.3 parallel input in data-through mode......................................................................... 24 4.2.4 parallel input clock (pclk) ............................................................................................ 25 4.3 smpte mode ................................................................................................................ ................... 26 4.3.1 hvf timing............................................................................................................... ........... 26 4.3.2 cea 861 timing........................................................................................................... ....... 28 4.4 dvb-asi mode .............................................................................................................. .................. 32 4.4.1 control signal inputs.................................................................................................... .... 32 4.5 data-through mode ......................................................................................................... ............ 33 4.6 standby mode .............................................................................................................. ................... 33 4.7 ancillary data insertion .................................................................................................. ............ 34 4.7.1 ancillary data insertion operating mode................................................................. 35 4.7.2 hanc insertion........................................................................................................... ....... 36 4.7.3 vanc insertion ........................................................................................................... ....... 36 4.8 additional processing functions ........................................................................................... ... 37 4.8.1 anc data blanking ........................................................................................................ ... 37 4.8.2 automatic video standard detection......................................................................... 37 4.8.3 video standard indication ............................................................................................. 38 4.8.4 packet generation and insertion.................................................................................. 39 4.9 parallel to serial conversion ............................................................................................. ......... 44 4.10 internal clockcleaner ? pll .................................................................................................... 45 4.10.1 external vco............................................................................................................ ........ 45 4.10.2 loop filter............................................................................................................. ............. 45 4.10.3 lock detect output...................................................................................................... ... 46
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 5 of 64 4.11 serial digital output .................................................................................................... .............. 46 4.11.1 output swing............................................................................................................ ........ 47 4.12 gspi host interface ...................................................................................................... ............... 47 4.12.1 command word descript ion ............... ........... ........... ........... ........... ........... ........... ..... 48 4.12.2 data read and write timing ....................................................................................... 49 4.12.3 configuration and status registers........................................................................... 50 4.13 jtag test operation ...................................................................................................... ............ 56 4.14 device reset ............................................................................................................. ..................... 58 5. application reference design ................................................................................................ ............... 59 5.1 typical application circuit ............................................................................................... ......... 59 6. references & relevant standards ............................................................................................. ............ 60 7. package & ordering information .............................................................................................. ............ 61 7.1 package dimensions ........................................................................................................ ............. 61 7.2 solder reflow profiles .................................................................................................... .............. 62 7.3 marking diagram ........................................................................................................... ................ 62 7.4 packaging data ............................................................................................................ ................... 63 7.5 ordering information ...................................................................................................... ............. 63 list of figures figure 3-1: differential output stage (sdo/sdo ) .............................................................................. 20 figure 3-2: charge pump current sett ing resistor (cp_res) .......................................................... 20 figure 3-3: pll loop filter ................................................................................................... ....................... 21 figure 3-4: vco input ......................................................................................................... ......................... 21 figure 3-5: digital input pin with weak pull up(>33kw) (pclk, din[19:0]) ............................................................................................................. ............................... 22 figure 3-6: 5v tolerant input pin (all other input pins) .................................................................. 22 figure 3-7: digital output pin with high impedance mode (locked, sdout_tdo) ........................................................................................................... ................... 22 figure 4-1: pclk to data timing ........................... .................................................................... ................ 24 figure 4-2: h_blanking, v_blanking, f_di gital timing .................................................................... 27 figure 4-3: hsync:vsync:de input ti ming 1280 x 720p @ 59.94/60 ....................................... 28 figure 4-4: hsync:vsync:de input timing 1920 x 1080i @ 59.94/60 ...................................... 29 figure 4-5: hsync:vsync:de input timing 720 (1440) x 480i @ 59.94/60 ............................. 30 figure 4-6: hsync:vsync:de input ti ming 1280 x 720p @ 50 ................................................... 31 figure 4-7: hsync:vsync:de input ti ming 1920 x 1080i @ 50 .................................................. 31 figure 4-8: hsync:vsync:de input ti ming 720 (1440) x 576 @ 50 ........................................... 32 figure 4-9: dvb-asi fifo implementation using the gs15 72 ....................................................... 33 figure 4-10: gennum serial pe ripheral interface (gspi) .................................................................. 48 figure 4-11: command word ..................................................................................................... ............... 48 figure 4-12: data word ........................................................................................................ ....................... 48 figure 4-13: gspi read mode timing ............................................................................................ ......... 49 figure 4-14: gspi write mode timing ....................... .................................................................... ......... 50 figure 4-15: in-circuit jtag .................................................................................................. .................... 57 figure 4-16: system jtag ..................................... ................................................................. ..................... 57 figure 4-17: reset pulse ...................................................................................................... ......................... 58 figure 7-1: maximum pb-free solder refl ow profile ......................................................................... 62
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 6 of 64 list of tables table 1-1: pin descriptions .................................................................................................... ........................ 8 table 2-1: absolute maximum ratings........................... ................................................................. ....... 16 table 2-2: recommended operating conditions................................................................................ 17 table 2-3: dc electrical characteristics ....................................................................................... .......... 17 table 2-4: ac electrical characteristics ....................................................................................... .......... 18 table 4-1: parallel data input format .......................................................................................... ........... 25 table 4-2: standby power consumption........................................................................................... ..... 34 table 4-3: host interface description for video standard register.............................................. 37 table 4-4: host interface description for raster structure registers........................................... 37 table 4-5: supported video standards ........................................................................................... ........ 38 table 4-6: host interface description for internal processing disable register....................... 40 table 4-7: host interface descriptio n for smpte 352m packet line number insertion registers ............................................................................................................ ............................. 41 table 4-8: host interface description for smpte 352m payload identifier registers ............ 41 table 4-9: host interface description for edh flag register (sd mode only).......................... 43 table 4-10: serial digital output rates........................................................................................ ........... 44 table 4-11: loop filter component values....................................................................................... .... 46 table 4-12: gspi timing parameters ............................................................................................. .......... 49 table 4-13: GS1572 internal registers .......................................................................................... .......... 50 table 4-14: configuration and status registers................ ................................................................. .. 51
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 7 of 64 1. pin out 1.1 pin assignment 1 3 2 45 6 7 8 9 10 a b c d e f g h j k lo c ked p c lk din1 6 din15 din14 din12 din10 din8 din 6 din4 din2 din1 din19 din13 din11 din9 din7 din5 din3 din0 s d/hd c p_vdd io_vdd an c _ io_vdd c ore _vdd io_ g nd c ore _vdd c ore _ g nd c ore _ g nd dete c t _tr s dvb_a s i s mpte_ bypa ss 20 b it/ 10 b it s din _tdi sc lk _t c lk s dout _tdo cs _ tm s c d_vdd r s et tim 8 6 1 r s v n c lf s do s do v c o_ v cc v c o_ g nd din17 v c o c d_ g nd pd_vdd r s v v/v s yn c io_ g nd c d_ g nd s tandby r s v r s v n c n c j ta g / ho s t s do_en/ di s re s et iopro c _en/di s r s v r s v n c n c r s v n c r s v r s v r s v din18 f/de v c o_ g nd c p_re s pd_vdd c ore _ g nd c ore _ g nd c ore _ g nd c ore _ g nd h/h s yn c c p_ g nd c d_ g nd c ore _ g nd c ore _ g nd c ore _ g nd c ore _ g nd c d_ g nd c ore _ g nd c ore _vdd c ore _ g nd c ore _vdd pd_ g nd pd_ g nd pd_ g nd r s v blank c ore _ g nd
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 8 of 64 1.2 pin descriptions table 1-1: pin descriptions pin number name timing ty p e description a1, a2, b1, b2, b3, c1, c2, c3, d1, d2 din[19:10] synchronous with pclk input parallel data bus signal levels are lvcmos/lvttl compatible. din19 is the msb and din10 is the lsb. hd 20-bit mode sd/hd = low 20bit/10bit = high luma data input in smpte mode smpte_bypass = high dvb_asi = low data input in data-through mode smpte_bypass = low dvb_asi = low hd 10-bit mode sd/hd = low 20bit/10bit = low multiplexed luma and chroma data input in smpte mode smpte_bypass = high dvb_asi = low data input in data-through mode smpte_bypass = low dvb_asi = low sd 20-bit mode sd/hd = high 20bit/10bit = high luma data input in smpte mode smpte_bypass = high dvb_asi = low data input in data-through mode smpte_bypass = low dvb_asi = low dvb-asi data input in dvb-asi mode smpte_bypass = low dvb_asi = high sd 10-bit mode sd/hd = high 20bit/10bit = low multiplexed luma and chroma data input in smpte mode smpte_bypass = high dvb_asi = low data input in data through mode smpte_bypass = low dvb_asi = low dvb-asi data input in dvb-asi mode smpte_bypass = low dvb_asi = high
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 9 of 64 a3 f/de synchronous with pclk input parallel data timing signal levels are lvcmos/lvttl compatible. tim_861 = low: used to indicate the odd / even field of the video signal when detect_trs is set low. the device will set the f bit in all outgoing trs signals for the entire period that the f input signal is high (ioproc_en/dis must also be high). the f signal should be set high for the entire period of field 2 and should be set low for all lines in field 1 and for all lines in progressive scan systems. the f signal is ignored when detect_trs = high. tim_861 = high: the de signal is used to indicate the active video period. de is high for active data and low for blanking. see section 4.3.1 and section 4.3.2 for timing details. the de signal is ignored when detect_trs = high. a4 h/hsync synchronous with pclk input parallel data timing signal levels are lvcmos/lvttl compatible. tim_861 = low: the h signal is used to indicate the portion of the video line containing active video data, when detect_trs is set low. active line blanking the h signal should be set high for the entire horizontal blanking period, including the eav and sav trs words, and low otherwise. this is the default setting. trs based blanking (h_config = 1 h ) the h signal should be set high for the entire horizontal blanking period as indicated by the h bit in the received trs id words, and low otherwise. the h signal is ignored when detect_trs = high. tim_861 = high: the hsync signal indicates horizontal timing. see section 4.3.1 for timing details. the hsync signal is ignored when detect_trs = high. a5, e1, g10, k8 core_vdd non synchronous input power power supply connection for the digi tal core logic. connect to +1.8v dc digital. a6, b6 pd_vdd analog input power power supply connection for the phase detector. connect to +1.8v dc analog. a7 lf analog input pll loop filter connection. a8 vco_vcc analog output power power supply for the external voltage controlled oscillator. 2.5v dc supplied by the device to the external vco. a9 vco analog input input from external vco. a10 cp_vdd analog input power power supply connection for the charge pump and on chip vco regulator. connect to +3.3v dc analog. table 1-1: pin descriptions (continued) pin number name timing ty p e description
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 10 of 64 b4 pclk C input parallel data bus clock signal levels are lvcmos/lvttl compatible. hd 20-bit mode pclk = 74.25mhz or 74.25/1.001mhz hd 10-bit mode pclk = 148.5mhz or 148.5/1.001mhz sd 20-bit mode pclk = 13.5mhz sd 10-bit mode pclk = 27mhz b5, c5, d5, e2, e5, e6, e7, f4, f5, f6, f7, g9, j8 core_gnd non synchronous input power ground connection for the digital core logic. connect to digital gnd. c6, c7, c8 pd_gnd analog input power ground connection for the phase detector. connect to analog gnd. b7 cp_res C input charge pump current setting resistor. b8, b9 vco_gnd analog output power ground pins for the vco. b10 cp_gnd analog input power ground pin for the charge pump and pll. c4 v/vsync synchronous with pclk input parallel data timing signal levels are lvcmos/lvttl compatible. tim_861 = low: the v signal is used to indicate the portion of the video field/frame that is used for vertical blanking, when detect_trs is set low. the v signal should be set high for the entire vertical blanking period and should be set low for all lines outside of the vertical blanking interval. the v signal is ignored when detect_trs = high. tim_861 = high: the vsync signal indicates vertical timing. see section 4.3.1 for timing details. the vsync signal is ignored when detect_trs = high. c9, d9, e9, f9 cd_gnd analog input power ground connection for the serial digital cable driver. connect to analog gnd. c10, d10 sdo, sdo analog output serial digital output signal operating at 1.485gb/s, 1.485/1.001gb/s, or 270mb/s. the slew rate of these outputs is automatically controlled to meet smpte 292m and 259m requirements according to the setting of the sd/hd pin. serial digital output signal fr om the internal cable driver. note: the sdo/sdo output signals will be set to high impedance when reset = low. table 1-1: pin descriptions (continued) pin number name timing ty p e description
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 11 of 64 d3 standby non synchronous input control signal input signal levels are lvcmos/lvttl compatible. power down input. when set high, the device will be in standby mode. d4 sdo_en/dis non synchronous input control signal input signal levels are lvcmos/lvttl compatible. used to enable or disable th e serial digital output stage. when set low, the serial digital output signals sdo and sdo are disabled and become high impedance. when set high, the serial digital output signals sdo and sdo are enabled. the sdo and sdo outputs will also be high impedance when the reset pin is low. d6, d7, d8, e4, e8, f8 nc C C no connect. not connected internally. e3 sd/hd non synchronous input control signal input signal levels are lvcmos/lvttl compatible. when set low, the device will be configured to transmit signals of 1.485gb/s - 1.485/1.001gb/s rates only. when set high, the device will be configured to transmit signals of a 270mb/s rate only. e10 cd_vdd analog input power power supply connection for the se rial digital cable driver. connect to +3.3v dc analog. f1, f2, h1, h2, j1, j2, j3, k1, k2, k3 din[9:0] synchronous with pclk input parallel data bus signal levels are lvcmos/lvttl compatible. din9 is the msb and din0 is the lsb. hd 20-bit mode sd/hd = low 20bit/10bit = high chroma data input in smpte mode smpte_bypass =high dvb_asi = low data input in data-through mode smpte_bypass = low dvb_asi = low hd 10-bit mode sd/hd = low 20bit/10bit = low high impedance in all modes. sd 20-bit mode sd/hd = high 20bit/10bit = high chroma data input in smpte mode smpte_bypass = high dvb_asi = low data input in data-through mode smpte_bypass = low dvb_asi = low forced low in dvb-asi mode smpte_bypass = low dvb_asi = high sd 10-bit mode sd/hd = high 20bit/10bit = low high impedance in all modes. table 1-1: pin descriptions (continued) pin number name timing ty p e description
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 12 of 64 f3 detect_trs non synchronous input control signal input signal levels are lvcmos/lvttl compatible. used to select external hvf timing mode or trs extraction timing mode. when detect_trs = low, the device will use timing from the externally supplied h:v:f or cea-861 timing signals, dependent on the state of the tim_861 pin. when detect_trs = high, the device will extract timing from trs signals embedded in the supplied video stream. f10 rset analog input an external 1% resistor co nnected to this input is used to set the sdo/sdo output amplitude. g1, h10 io_vdd non synchronous input power power supply connection for digital i/o buffers. connect to +3.3v or +1.8v dc digital. g2, h9 io_gnd non synchronous input power ground connection for digital i/o buffers. connect to digital gnd. g3 tim_861 non synchronous input control signal input signal levels are lvcmos/lvttl compatible. used to select external cea-861 timing mode. when detect_trs = low and tim_861 = low, the device will use externally supplied h:v:f timing signals. when detect_trs = low and tim_861 = high, the device will use externally supplied hsync, vsync, de timing signals. when detect_trs = high, the device will extract timing from trs signals embedded in the supplied video stream. g4 20bit/10bit non synchronous input control signal input signal levels are lvcmos/lvttl compatible. used to select the input data bus width. g5 dvb_asi non synchronous input control signal input signal levels are lvcmos/lvttl compatible. when set high, the device is co nfigured for the transmission of dvb-asi data in sd mode (sd/hd = high). when set low, the device will not support the encoding of dvb-asi data. note: when operating in dvb-asi mode the sd/hd pin must be set high and smpte_bypass must be set low. g6 smpte_bypass non synchronous input control signal input signal levels are lvcmos/lvttl compatible. used to enable/disable all forms of encoding/decoding, scrambling and edh insertion. when set low, the device will operate in data through mode (dvb_asi = low), or in dvb-asi mode (dvb_asi = high). no smpte scrambling will take place and none of the i/o processing features of the device will be available when smpte_bypass is set low. when set high, the device will perform smpte scrambling and i/o processing. table 1-1: pin descriptions (continued) pin number name timing ty p e description
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 13 of 64 g7 ioproc_en/dis non synchronous input control signal input signal levels are lvcmos/lvttl compatible. used to enable or disable i/o processing features. when set high, the following i/o processing features of the device are enabled: ? edh packet generation and insertion (sd-only) ? smpte 352m packet generation and insertion ? anc data checksum calculation ? anc data insertion ? line-based crc generation and insertion (hd-only) ? line number generation and insertion (hd-only) ? trs generation and insertion ? illegal code remapping to enable a subset of these features, set ioproc_en/dis = high and disable the individual feature(s) in the ioproc_disable register accessible via the host interface. when set low, the i/o processing features of the device are disabled, and can not be enabled by changing the settings in the ioproc_disable register. g8 reset non synchronous input control signal input signal levels are lvcmos/lvttl compatible. used to reset the internal operat ing conditions to default settings and to reset the jtag test sequence. normal mode (jtag/host = low) when set low, all functional blocks will be set to default conditions and all input and output signals become high impedance including the serial digital outputs sdo and sdo. when set high, normal operatio n of the device resumes 10usec after the low to high transition of the reset signal. jtag test mode (jtag/host = high) when set low, all functional blocks will be set to default and the jtag test sequence will be held in reset. when set high, normal operation of the jtag test sequence resumes. h3 anc_blank non synchronous input control signal input signal levels are lvcmos/lvttl compatible. used to enable or disable anc data blanking. when set low, the hanc and vanc data is mapped to the appropriate blanking levels. table 1-1: pin descriptions (continued) pin number name timing ty p e description
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 14 of 64 h4 locked synchronous with pclk output status signal output signal levels are lvcmos / lvttl compatible. this signal is set high by the device when the internal pll has achieved lock to the supplied pclk signal. this pin is set low by the device under all other conditions. io_vdd = 3.3v drive strength = 8ma io_vdd = 1.8v drive strength = 4ma h5, h6, h7, j4, j5, j6, j7, k4, k5, k6, k7 rsv non synchronous input reserved. do not connect. h8 jtag/host non synchronous input control signal input signal levels are lvcmos/lvttl compatible. used to select jtag test mode or host interface mode. when set high, cs _tms, sdout_tdo, sdi_tdi and sclk_tck are configured for jtag boundary scan testing. when set low, cs _tms, sdout_tdo, sdi_tdi and sclk_tck are configured as gennum serial peripheral interface (gspi) pins for normal host interface operation. j9 sdout_tdo synchronous with sclk_tck output communication signal output signal levels are lvcmos/lvttl compatible. serial data output / test data output host mode (jtag/host = low) this pin operates as the host interface serial output, used to read status and configuration informatio n from the internal registers of the device. jtag test mode (jtag/host = high) this pin is used to shift test results and operates as the jtag test data output, tdo. note: if the host interface is not being used leave this pin unconnected. drive strength: io_vdd = 3.3v = 12ma io_vdd = 1.8v = 4ma j10 sclk_tck non synchronous input communication signal input signal levels are lvcmos/lvttl compatible. serial data clock / test clock. host mode (jtag/host = low) sclk_tck operates as the host interface burst clock, sclk. command and data read/write words are clocked into the device synchronously with this clock. jtag test mode (jtag/host = high) this pin is the test mode start pin, used to control the operation of the jtag test clock, tck. note: if the host interface is not being used, tie this pin high. table 1-1: pin descriptions (continued) pin number name timing ty p e description
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 15 of 64 k9 cs_tms synchronous with sclk_tck input communication signal input signal levels are lvcmos/lvttl compatible. chip select / test mode start. host mode (jtag/host = low) cs _tms operates as the host interface chip select, cs , and is active low. jtag test mode (jtag/host = high) cs _tms operates as the jtag test mode start, tms, used to control the operation of the jtag test, and is active high. note: if the host interface is not being used, tie this pin high. k10 sdin_tdi synchronous with sclk_tck input communication signal input signal levels are lvcmos/lvttl compatible. serial data in / test data input host mode (jtag/host = low) this pin operates as the host interface serial input, sdin, used to write address and configuration information to the internal registers of the device. jtag test mode (jtag/host = high) this pin is used to shift and operates as the jtag test data input, tdi. note: if the host interface is not being used, tie this pin high. table 1-1: pin descriptions (continued) pin number name timing ty p e description
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 16 of 64 2. electrical characteristics 2.1 absolute maximum ratings table 2-1: absolute maximum ratings parameter value/units supply voltage, core (core_vdd) -0.3v to +2.1v supply voltage, analog 1.8v (pd_vdd) -0.3v to +2.1v supply voltage, i/o (io_vdd) -0.3v to +3.6v supply voltage, analog 3.3v (cp_vdd, cd_vdd) -0.3v to +3.6v input voltage range (pclk, din) -0.5v to io_vdd+0.25v input voltage range (vco, cp_res, lf, rset) -0.5v to +3.6v input voltage range (all other pins) -0.5v to +5.25v ambient operating temperature -40c < t a < 95c storage temperature -40c < t stg < 125c peak reflow temperature (jedec j-std-020c) 260c esd sensitivity, hbm (jesd22-a114) 4000v esd sensitivity, mm (jesd22-a115) 200v notes: 1. absolute maximum ratings ar e those values beyond which damage may occur. functional operation under these conditions or at any other condition beyond those indicated in the ac/dc electrical characteristics sections is not implied.
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 17 of 64 2.2 recommended operating conditions 2.3 dc electrical characteristics table 2-2: recommended operating conditions parameter symbol conditions min ty p max units notes operating temperature range, ambient t a C -20 25 85 c supply voltage, digital core core_vdd C 1.71 1.8 1.89 v supply voltage, phase detector pd_vdd C 1.71 1.8 1.89 v supply voltage, charge pump cp_vdd C 3.13 3.3 3.47 v supply voltage, cable driver cd_vdd C 3.13 3.3 3.47 v supply voltage, digital i/o io_vdd 1.8v mode 1.71 1.8 1.89 v supply voltage, digital i/o io_vdd 3.3v mode 3.13 3.3 3.47 v table 2-3: dc electrical characteristics parameter symbol conditions min ty p max units notes system external vco power supply voltage (vco_vdd) 2.375 2.5 2.625 v 1 +1.8v supply current i 1v8 10/20bit hd C 109 130 ma 2,4 10/20bit sd C 104 120 ma 2,4 dvb_asi C 100 120 ma 2,4 +3.3v supply current i 3v3 10/20bit hd C 74 86 ma 3,4 10/20bit sd C 74 86 ma 3,4 dvb_asi C 74 86 ma 3,4 total device power p d 10/20bit hd C 440 540 mw 4 10/20bit sd C 430 530 mw 4 dvb_asi C 424 510 mw 4 reset C 310 C mw C standby 10 125 C mw 5
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 18 of 64 2.4 ac electrical characteristics digital i/o input logic low v il 3.3v or 1.8v operation C C 0.3 x io_vdd vC input logic high v ih 3.3v or 1.8v operation 0.7 x io_vdd CCvC output logic low v ol 1.8v mode C C 0.3 v C 3.3v mode C C 0.4 v C output logic high v oh 1.8v mode 1.4 C C v C 3.3v mode 2.4 C C v C output output common mode voltage v cmout 75 load, rset=750 sd and hd mode C cd_vdd - v sdd CvC notes 1. vco_vdd guaranteed only when go1555 is connected. 2. sum of all 1.8v supplies. 3. sum of all 3.3v supplies. 4. io_vdd = 3.3v. when io_vdd = 1.8v, the curren t/power consumption is lower by up to 5ma/10mw. 5. see 4.6 standby mode for details. table 2-3: dc electrical characteristics parameter symbol conditions min ty p max units notes table 2-4: ac electrical characteristics parameter symbol conditions min ty p max units notes system device latency C C C C 27 pclk C C dvb-asi C C 15 pclk C reset pulse width t reset C10CCms1 parallel input parallel clock frequency f pclk C 13.5 C 148.5 mhz C parallel clock duty cycle dc pclk C40C 60%C input data setup time t su 50% levels; 3.3v or 1.8v operation 2C Cns 4 input data hold time t ih 0.8 C C ns 4 serial digital output serial output data rate dr sdo C C 1.485 C gb/s C C C 1.485/1.001 C gb/s C C C 270 C mb/s C serial output swing v sdd rset = 750 75 load 750 800 850 mvp-p C
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 19 of 64 serial output rise/fall time 20% ~ 80% trf sdo hd mode C 120 270 ps C trf sdo sd mode 400 660 800 ps C mismatch in rise/fall time t r , t f CCC35psC duty cycle distortion C C C 1 5 % 5 overshoot C sd/hd =0 C 5 10 % 5 C sd/hd =1 C 3 8 % 5 output return loss orl 5 mhz - 1.485 ghz C 18 C db 6 serial output intrinsic jitter t oj pseudorandom and smpte colour bars hd signal C3580ps 2 t oj pseudorandom and smpte colour bars sd signal C 100 200 ps 3 gspi gspi input clock frequency f sclk 50% levels 3.3v or 1.8v operation CC10mhz C gspi input clock duty cycle dc sclk 40 50 60 % C gspi input data setup time C 1.5 C C ns C gspi input data hold time C 1.5 C C ns C gspi output data hold time C 15pf load 1.5 C C ns C cs low before sclk rising edge C 50% levels 3.3v or 1.8v operation 1.5 C C ns C time between end of command word (or data in auto-increment mode) and the first sclk of the following data word - write cycle C 50% levels 3.3v or 1.8v operation 37.1 C C ns C time between end of command word (or data in auto-increment mode) and the first sclk of the following data word - read cycle C 50% levels 3.3v or 1.8v operation 148.4 C C ns C cs high after sclk rising edge C 50% levels 3.3v or 1.8v operation 37.1 C C ns C notes: 1. see device reset on page 58, figure 4-17 . 2. alignment jitter = measur ed from 100khz to 148.5mhz 3. alignment jitter = measured from 1khz to 27mhz 4. input setup and hold time is de pendent on the rise and fall time on the parallel input . parallel clock and data with rise tim e or fall time greater than 500ps require larger setup and hold times. 5. single ended into 75 external load. 6. orl depends on board design. the GS1572 achieves this specificati on on gennums evaluation boards. table 2-4: ac electrical characteristics parameter symbol conditions min ty p max units notes
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 20 of 64 3. input/output circuits all resistors in ohms, all capacitors in farads, unless otherwise shown. figure 3-1: differential output stage (sdo/ sdo ) figure 3-2: charge pump current setting resistor (cp_res) c d_vdd i ref s do s do cp_res 200 800mv
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 21 of 64 figure 3-3: pll loop filter figure 3-4: vco input 800 800 vdd 5.6k 5.6k vdd lf 50 50 40k 160k vdd 50pf vco
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 22 of 64 figure 3-5: digital input pin with weak pull up(>33k ) (pclk, din[19:0]) figure 3-6: 5v tolerant inpu t pin (all other input pins) figure 3-7: digital output pin with high impedance mode (locked, sdout_tdo) io_vdd input pin input pin io_vdd output pin en
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 23 of 64 4. detailed description 4.1 functional overview the GS1572 is a multi-rate serializer with an integrated cable dr iver. when used in conjunction with the external go1555 voltage controlled oscillator, a transmit solution at 1.485gb/s, 1.485/1.001gb/s or 270mb/s is realized. the device has three basic modes of operation that must be set through external device pins: smpte mode, dvb-asi mo de and data-through mode. in smpte mode, the device will accept 10- bit multiplexed or 20-bit demultiplexed smpte compliant data at both hd and sd signal rates. by default, the device?s additional processing features will be enabled in this mode. in dvb-asi mode, the GS1572 wi ll accept an 8-bit parallel dvb-asi compliant transport stream on din[17:10]. the serial output data stream will be 8b/10b encoded with stuffing characters added as per the standard. data-through mode allows for the serializing of data not conforming to smpte or dvb-asi streams. no additional processing will be done in this mode. in standby mode, the device power consumption will be reduced. the serial digital output features a high-imp edance mode and adjustable signal swing. the output slew rate is automatically set by the sd/hd pin setting. GS1572 provides several data processing function s including generic anc insertion, smpte 352m and edh data packet generation and insertion, automatic video standards detection, and trs, crc, anc data checksum, and line number calculation and insertion. these features are all enabled/disa bled collectively by us ing the external io processing pin, but may be individually disabled via internal registers accessible through the gspi host interface. finally, the GS1572 contains a jtag interfac e for boundary scan test implementations. 4.2 parallel data inputs data is clocked into the device on th e rising edge of pclk as shown in figure 4-1 . the input data format is defined by the setting of the external sd/hd , smpte_bypass , and dvb_asi pins and may be presented in 10-bit or 20-bit format. the input data bus width is controlled by the 20bit/10bit input pin.
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 24 of 64 figure 4-1: pclk to data timing 4.2.1 parallel input in smpte mode when the device is operating in smpte mode, see smpte mode on page 26 , both sd and hd data may be presented to the input bus in either multiplexed or demultiplexed form depending on the setting of the 20bit/10bit input pin. in 20-bit mode, (20bit/10bit = high), the input data format should be word aligned, demultiplexed luma and chroma data. luma words should be presented on din[19:10] while chroma words should be presented on din[9:0]. in 10-bit mode, (20bit/10bit = low), the input data format should be word aligned, multiplexed luma and chroma data. the data should be presented on din[19:10]. din[9:0] will be high-imp edance in this mode. 4.2.2 parallel input in dvb-asi mode when operating in dvb-asi mode, see dvb-asi mode on page 32 , the GS1572 must be set to 10-bit operation mode by setting the 20bit/10bit pin low. the device will accept 8-bit data words on din[17:10] such that din17 = hin is the most significant bit of the encoded transport stream data and din10 = ain is the least significant bit. in addition, din19 and din 18 will be configured as the dvb-asi control signals inssyncin and kin respectively. see dvb-asi mode on page 32 for a description of these dvb-asi specific input signals. din[9:0] will have a logic level high in dvb-asi mode. 4.2.3 parallel input in data-through mode when operating in data-through mode, see data-through mode on page 33 , the GS1572 passes data from the pa rallel input bus to the serial output withou t performing any encoding or scrambling. the input data bus width is controlled by the setting of the 20bit/10bit pin. p c lk din[19:0] data c ontrol s i g nal input t s u t ih
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 25 of 64 4.2.4 parallel input clock (pclk) the frequency of the pclk input signal requ ired by the GS1572 is determined by the input data format. table 4-1 below lists the possible input signal formats and their corresponding parallel clock rates. note that dvb-asi input will only be in 10-bit format, when setting the 20bit/10bit pin low. table 4-1: parallel data input format input data format din [19:10] din [9:0] pclk control signals 20bit/ 10bit sd/ hd smpte_bypass dvb_asi smpte mode 20-bit demultiplexed sd luma chroma 13.5mhz high high high low 10-bit multiplexed sd luma/ chroma high impedance 27mhz low high high low 20-bit demultiplexed hd luma chroma 74.25 or 74.25/ 1.001mhz high low high low 10-bit multiplexed hd luma/ chroma high impedance 148.5 or 148.5/ 1.001mhz low low high low dvb-asi mode 10-bit dvb-asi dvb-asi data high impedance 27mhz low high low high low high low high data-through mode 20-bit sd data data 13.5mhz high high low low 10-bit sd data high impedance 27mhz low high low low 20-bit hd data data 74.25 or 74.25/ 1.001mhz high low low low 10-bit hd data high impedance 148.5 or 148.5/ 1.001mhz low low low low
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 26 of 64 4.3 smpte mode the GS1572 operates in smpte mode when the smpte_bypass pin is set high and the dvb_asi pin is set low. in this mode, the parallel da ta will be scrambled accordin g to smpte 259m or 292m, and nrz-to-nrzi encoded prior to serialization. 4.3.1 hvf timing in smpte mode, the GS1572 can automatically detect the video stan dard and generate all internal timing signals. the total line length, active line length, total number of lines per field/frame and total active lines per field/frame are calculated for the received parallel video. when detect_trs is low, the video standa rd and timing signals are based on the externally supplied h_blanking, v_blanking, and f_digital signals. these signals go to the h/hsync, v/vsync, and f/de pins resp ectively. when detect_trs is high, the video standard timing signals will be extracted from the embedded trs id words in the parallel input data. both 8-bit and 10-bit trs code words will be identified by the device. note: i/o processing must be enabled for the device to remap 8-bit trs words to the corresponding 10-bit value for transmission. see section 4.8.4.2 for more information. the GS1572 determines the video standard by timing the horizontal and vertical reference information supplied at the h/hs ync, v/vsync, and f/de input pins, or contained in the trs id words of the received video data. therefore, full synchronization to the received video standard requires one complete video frame. once synchronization has been achieved, the GS1572 will continue to monitor the received trs timing or the supplied h, v, and f timing information to maintain synchronization. GS1572 will lose all timing information immediatel y following loss of h, v and f. the h signal timing should also be configured via the h_config bit of the internal ioproc_disable register as either active line based blanking or trs based blanking. see packet generation and insertion on page 39 . active line based blanking is enabled when the h_config bit is set low. in this mode, the h input should be high for the entire horizontal blanking period, including the eav and sav trs words. this is the defa ult h timing used by the device. the timing of these signals is shown in figure 4-2 .
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 27 of 64 figure 4-2: h_blanking, v_ blanking, f_digital timing h_blankin g : v_blankin g : f_di g ital timin g - hd 20-bit input mode p c lk luma data out c hroma data out h xyz (eav) 000 000 3ff xyz (eav) 000 000 3ff v f xyz (sav) 000 000 3ff xyz (sav) 000 000 3ff h_blankin g : v_blankin g : f_di g ital timin g at s av - hd 10-bit input mode 000 000 3ff 3ff xyz (sav) 000 000 xyz (sav) p c lk h v f h_blankin g : v_blankin g : f_di g ital timin g at eav - hd 10-bit input mode p c lk 000 000 3ff 3ff xyz (eav) 000 000 xyz (eav) multiplexed y/ c r/ cb data out h v f multiplexed y/ c r/ cb data out h_blankin g : v_blankin g : f_di g ital timin g - s d 20-bit input mode p c lk c hroma data out luma data out h 000 3ff xyz (eav) 000 v f 000 3ff xyz ( s av) 000 h_blankin g : v_blankin g : f_di g ital timin g - s d 10-bit input mode multiplexed y/ c r/ cb data out p c lk h v f xyz (eav) 000 000 3ff xyz (sav) 000 000 3ff h s i g nal timin g : h_ c onfi g = low h_ c onfi g = hi g h
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 28 of 64 4.3.2 cea 861 timing the GS1572 extracts timing information from externally provided hsync, vsync, and de signals when cea 861 timing mode is selected by setting detect_trs = low and tim_861 = high. horizontal sync (h), vertical sync (v), and data enable (de) timing must be provided via the h/hsync, v/vsync and f/de input pins. the host interface register bit h_config will be ignored in the cea 861 input timing mode. the GS1572 will determine th e eia/cea-861 standard an d embed eav and sav trs words in the output serial video stream. video standard detection is not dependent on the hsync pulse width or the vsync pulse width and therefore the GS1572 will to lerate non-standard pulse widths. in addition, the device can compensate for up to 1 pclk cycle of jitter on vsync with respect to hsync and sa mple vsync correctly. note 1: the period between the leading edge of the hsync pulse and the leading edge of data enable (de) must follow the timing requirements described in the eia/cea-861 specification. the GS1572 embeds trs words according to this timing relationship to maintain compatibility with the corresponding smpte standard. note 2: when cea 861 standards 6 & 7 [ 720(1440)x480i] are presen ted to the GS1572, the device will embed trs wo rds corresponding to the ti ming defined in smpte 125m to maintain smpte compatibility. cea 861 standards 6 & 7 [720(1440)x480i] define the active area on lines 22 to 261 and 285 to 524 inclusive (240 active lines per fi eld). smpte 125m defines the active area on lines 20 to 263 and 283 to 525 inclusive (244 lines on field 1; 243 lines on field 2). therefore, in the first field, the GS1572 adds two active lines above and two active lines below the original active image. in the second field it adds two lines above and one line below the original active image. figure 4-3: hsync:vsync:de i nput timing 1280 x 720p @ 59.94/60 1980 clocks 440 hsync vsync 720 active vertical lines data enable 745 746 747 748 749 750 1 2 3 4 5 6 7 25 26 745 746 750 progressive frame: 30 vertical blanking lines 1980 total horizontal clocks per line data enable hsync 40 1280 clocks for active video 700 440 220 clocks ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 29 of 64 figure 4-4: hsync:vsync:de input timing 1920 x 1080i @ 59.94/60 2200 total horizontal clocks per line data enable hsync 44 1920 clocks for active video 280 88 148 clocks 2200 clocks 88 hsync vsync 540 active vertical lines per field data enable 1123 1124 1125 1 2 3 4 5 6 7 8 19 20 21 560 561 562 field 1: 22 vertical blanking lines 1100 2200 clocks 88 hsync vsync 540 active vertical lines per field data enable 560 561 562 563 564 565 566 567 568 569 570 582 583 584 1123 1124 1125 field 2: 23 vertical blanking lines ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 30 of 64 figure 4-5: hsync:vsync:de input timing 720 (1440) x 480i @ 59.94/60 1716 total horizontal clocks per line data enable hsync 124 1440 clocks for active video 276 38 114 clocks 1716 clocks 38 hsync vsync 240 active vertical lines per field data enable 524 525 1 2 3 4 5 6 7 8 9 21 22 261 262 263 field 1: 22 vertical blanking lines 858 1716 clocks hsync vsync data enable 261 262 263 264 265 266 267 268 269 270 271 284 285 524 525 1 field 2: 23 vertical blanking lines ~ ~ ~ ~ ~ ~ ~ ~ 238 238 ~ ~ ~ ~ ~ ~ ~ ~ 240 active vertical lines per field
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 31 of 64 figure 4-6: hsync:vsync:de input timing 1280 x 720p @ 50 figure 4-7: hsync:vsync:de input timing 1920 x 1080i @ 50 1650 cl ocks 110 hsync vsync 720 active vertical lines data enable 745 746 747 748 749 750 1 2 3 4 5 6 7 25 26 745 746 750 progressive frame: 30 vertical blanking lines 1650 total horizontal clocks per line data enable hsync 40 1280 clocks for active video 370 110 220 clocks ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 2640 total horizontal clocks per line data enable hsync 44 1920 clocks for active video 720 528 148 clocks 2640 clocks 528 hsync vsync 540 active vertical lines per field data enable 1123 1124 1125 1 2 3 4 5 6 7 8 19 20 21 560 561 562 field 1: 22 vertical blanking lines 1320 2640 clocks 528 hsync vsync 540 active vertical lines per field data enable 560 561 562 563 564 565 566 567 568 569 570 582 583 584 1123 1124 1125 field 2: 23 vertical blanking lines ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 32 of 64 figure 4-8: hsync:vsync:de i nput timing 720 (1440) x 576 @ 50 4.4 dvb-asi mode the GS1572 operates in dvb-asi mode when the smpte_bypass pin is set low and the dvb_asi and sd/hd pins are set high. in this mode, all smpte processing functions are disabled, and the 8-bit transport stream data will be 8b/10b encoded prior to serialization. 4.4.1 control signal inputs in dvb-asi mode, the din19 and din18 pins are configured as dvb-asi control signals inssyncin and kin respectively. when inssyncin is set high, the device will insert k28.5 sync characters into the data stream. this func tion is used in system implemen tations where the GS1572 is preceded by an external data fifo. pa rallel dvb-asi data may be cloc ked into the fifo at some rate less than 27mhz. the inssyncin input may then be connected to the fifo empty signal, providing a means of padding the data transmission rate to 27mhz. see figure 4-9 . 1728 total horizontal clocks per line data enable hsync 126 1440 clocks for active video 288 24 138 clocks 1728 clocks 24 hsync vsync 288 active vertical lines per field data enable 623 624 625 1 2 3 4 5 6 7 22 23 310 311 312 field 1: 24 vertical blanking lines 864 1728 clocks hsync vsync data enable 310 311 312 313 314 315 316 317 318 319 320 335 336 623 624 625 field 2: 25 vertical blanking lines ~ ~ ~ ~ ~ ~ ~ ~ 264 264 ~ ~ ~ ~ ~ ~ ~ ~ 288 active vertical lines per field
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 33 of 64 note: 8b/10b encoding will take place after k28.5 sync character insertion. kin should be set high whenever the parallel data input is to be interpreted as any special character defined by the dvb-asi stan dard (including the k28.5 sync character). this pin should be set low when the input is to be interpreted as data. note: when operating in dvb-asi mode, din[9:0] will have a logic level high. figure 4-9: dvb-asi fifo impl ementation using the GS1572 4.5 data-through mode the GS1572 may be configured to operate as a si mple parallel-to-serial converter. in this mode, the device passes data to the serial output without performing any scrambling or encoding. data-through mode is enabled on ly when both the smpte_bypass and dvb_asi pins are set low. 4.6 standby mode in standby mode, the power consumption of the GS1572 is reduced to 125mw. standby mode is enabled when the standby pin is set high. once the standby pin is set high, it may take up to 50ms for power reduction to take place. in this mode, the serial output pins are se t to high-impedance and the GS1572 loses lock to the reference input pclk. while in standby mode, the programmed register values are retained. however, no registers can be ac cessed for reading or writing via the gspi port. no write bits will be captured and all read functions will return a value of zero. the power in standby mode can be further reduced through two means: 1. eliminate activity on all parallel data and clock inputs. this can be achieved by setting the parallel data and clock high or not driving them. setting the parallel inputs to low is not recommended, as it will result in a smaller power saving. 2. remove the 3.3v supply to the cd_vdd pin of the device. the standby power consumption under various conditions is shown in table 4-2: standby power consumption . in order to return to normal operation from standby mode, the standby pin must be set to low. once normal oper ation mode is resumed, the GS1572 will re-lock to the 8 8 ain ~ hin p c lk = 27mhz in ss yn c in s do c lk_in c lk_out fifo s do write_ c lk <27mhz fifo_empty t s kin gs 1572 kin read c lk =27mhz
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 34 of 64 reference pclk. the recovery time from standby mode is the same as initial power-up but no reset is required. once GS1572 re-locks to the reference pclk, operation is resumed according to the configuration held before entering standby mode. 4.7 ancillary data insertion horizontal or vertical ancillary data words may be inserted on up to four different lines per video frame. in order to insert hanc da ta, the anc_type bit in the host interface, must be set low. vanc data can be inserted by setting the anc_ty pe bit in the host interface high. by default, at power up, hanc data insertion is selected. the user must write the ancillary data words to be inserted, the line number for the insertion, and the total number of words to be inserted to the designated registers in the host interface. at power up, or after system reset, all anc data insertion line numbers and total number of words default to zero. all data words including the ancillary packet adf, dbn, dc, did, sdid, and checksum (placeholder) must be provided. the user provided checksum word is a placeholder. the correct value will be calculated and inserted automatically. two modes of operation are provided; separate line mode and concatenated mode. by default, at power up or after system reset, separate line operating mode is selected. the GS1572 ancillary data inse rtion provides no error ch ecking or correction. the provided ancillary data must be fully smpte compliant. the packet_missed bit in the host interface is set if: ? an ancillary data packet is only partially inserted because there is no more free space in the hanc or vanc region of the selected line ? an ancillary data packet is not inserted at all because there is no free space in the hanc or vanc region of the selected line ? the number of words to insert programmed through the host interface is greater than the maximum allowed for the operating mode (128 in separate line mode or 512 in concatenated li ne mode). under this condition, the bit will be set once the maximum number has been reached table 4-2: standby power consumption standby condition typical power consumption (mw) standby asserted 125 standby asserted parallel data and clock inactive 100 standby asserted 3.3v supply removed from cd_vdd 35 standby asserted parallel data and clock inactive 3.3v supply removed from cd_vdd <10
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 35 of 64 this bit is cleared once per frame on the rising edge of v or when it is read through the host interface. in sd mode, the ancillary data packets are inserted into the multiplexed ycbcr video stream. in hd mode, by defaul t ancillary data packets will be inserted into the luma channel. insertion in the chroma channel may be selected via the host interface. ancillary data insertion in the luma and chroma channels can be selected on a per line basis. ancillary data insertion only takes place if the ioproc_en/dis pin is set high, smpte_bypass is set high, and the anc_ins bit in the ioproc_disable register is set low. note 1: it is good practice to program th e ancillary data words prior to programming the line number and number of words. ancillary data insertion only begins once the line number and number of words are set to a non-zero value. therefore, this practice ensures that no data is written to the anc space before the programming is complete. as such, no unintended data is written to the anc space even if the programmed line number is reached before the programming is complete. also, read/write conflicts are avoided. it is recommended to finish programming all the data at least 1 line prior to where ancillary data insertion is to begin. note 2: in both separate line mode and concatenated mode, more than one ancillary data packet may be inserted per line. the user provided ancillary data packets must contain a checksum place holder word. the correct checksum for each packet will then be re-calculated and inserted by GS1572. the total number of words for all the provided ancillary data packets with checksum should not exceed 128 in sepa rate line mode and 512 in concatenated mode. 4.7.1 ancillary data in sertion operating mode 4.7.1.1 separate line mode in separate line mode, it is po ssible to insert horizontal or vertical ancillary data on up to four lines per video frame. for each of the four vi deo lines, up to 128 8-bit hanc or vanc data words can be inserted. separate line mode is selected by setting the anc_ins_mode bit in the host interface low. by default, at power up, separate line mode is selected. the non-zero video line numbers on which to insert the ancillary data, the ancillary data type (hanc or vanc), and the total number of words to insert per line must be provided via the host interface. at power up, or after system reset, all ancillary data insertion line numbers and total number of words default to zero. if the total number of data words specifie d per line exceeds 128 on ly the first 128 data words will be inserted. the device automatically converts the provided 8-bit data words into the 10-bit data, formatted according to smpt e 291m prior to insertion.
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 36 of 64 4.7.1.2 concatenated mode in concatenated mode, it is po ssible to insert up to 512 8-bit horizontal or vertical ancillary data words on one line per video frame. concatenated line mode can be selected by setting the anc_ins_mode bit in the host interface high. by default, at power up, separate line mode is selected. the non-zero video line number on which to insert the ancillary data, the ancillary data type (hanc or vanc), and the total number of words to insert must be provided via the host interface. at power up, or after system reset, the ancillary data insertion line number and total number of words default to zero. if the total number of data words specified exceeds 512 only the first 512 data words will be inserted. the device automatically converts the provided 8-bit data words into the 10-bit data formatted according to smpt e 291m prior to insertion. 4.7.2 hanc insertion by default, at power up or after system reset, all ancillary data is inserted in the hanc space. data is inserted contiguously starting at the trs eav or the first available location following any pre-existing ancillary data packets. data insertion terminates when all provided data words have been inserted or at the start of the trs sav code, whichever occurs first. if termination occurs be fore all words have been inserted, the packet_missed bit will be se t in the host interface. note 1: edh packet insertion in sd mode occurs following ancillary data insertion. thus, any hanc data inserted on the same line as the edh packet may be overwritten during edh insertion. when hanc data is inserted on an edh line, the packet_missed bit may be erroneously set, even though the ancillary data packet has been inserted correctly. note 2: hanc space ancillary data header s undergo 8-bit to 10- bit remapping. this means that when the 8 msbs are all zero, the value gets mapped to 000 and when the 8 msbs are all 1, the value gets mapp ed to 3ff. (i.e. 000, 001, 002, 003 ??> 000 and 3fe, 3fd, 3fc ??> 3ff) 4.7.3 vanc insertion ancillary data insertion into the vanc space can be selected via the host interface. data is inserted contiguously starting at the trs sav or the first available location following any pre-existing ancillary data packets. data insertion terminates when all provided data words have been inserted or at the start of the trs eav code, whichever occurs first. if termination occurs before all words have been inserted, the packet_missed bit will be set in the host interface. note: when ancillary data is inserted into the active region of the video raster using the vanc feature, if the illegal_ remap in the ioproc_disable re gister bit is set to zero, then the adfs are remapped to '004 | 3fb | 3fb' and the downstream devices will not detect the ancillary data packets.
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 37 of 64 4.8 additional processing functions the GS1572 incorporates additi onal data processing which is available in smpte mode only, see smpte mode on page 26 . 4.8.1 anc data blanking the horizontal and vertical ancillary spaces of the input video may be 'blanked' by the GS1572. in this mode, the trs words and active video will be preser ved. any additional processing functions, including ancillary data insertion, occur after blanking and will be present in the output video stream. this function is enabled by setting the anc_blank pin low. 4.8.2 automatic video standard detection the GS1572 can detect the input video stan dard by using the timing pa rameters extracted from the received trs id words, the supplied h_blanking, v_blanking, and f_digital timing signals, or the cea 861 timing signals, see hvf timing on page 26 and cea 861 timing on page 28 . this information is presented in the video_standard register ( table 4-3 ). total samples per line, active samples per line, total lines per field/frame and active lines per field/frame are also calculated and av ailable via the raster_structure registers ( table 4-4 ). these line and sample count registers are updated once per frame at the end of line 12. after device reset, the four raster_ structure registers default to zero. table 4-3: host interface description for video standard register register name bit name description r/w default video_standard address: 004h 15 C not used. C C 14-10 vd_std[4:0] video data standard (see table 4-5 ). r 0 9int_prog interlace/progressive: set low if detected video standard is progressive and is set high if it is interlaced. r0 8 std_lock standard lock: set high when the device has achieved full synchronization. r0 7-0 C not used. C C table 4-4: host interface descript ion for raster structure registers register name bit name description r/w default raster_structure1 address: 00eh 15-12 C not used. C C 11-0 raster_structure_1[11:0] words per active line r 0 raster_structure2 address: 00fh 15-13 C not used. C C 12-0 raster_structure_2[12:0] words per total line. r 0
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 38 of 64 4.8.3 video standard indication the value reported in the vd_std[4:0] bits of the video_standard register corresponds to the smpte standards as shown in table 4-5 . in addition to the 5-bit video standard code word, the video_standard register also contains two status bits. the std_lock bit will be set high whenever the device has achieved full synchronization. the int_prog bit will be set low if the detected video standard is progressive and high if the detected video standard is interlaced. the vd_std[4:0], std_lock and int_prog bits of the video_standard register will default to zero after device reset. the vd_std[4:0] and int_prog bits will also default to zero if the smpte_bypass pin is asserted low. the std_lock bit will retain its previous value if the pclk is removed. raster_structure3 address: 010h 15-11 C not used. C C 10-0 raster_structure_3[10:0] total lines per frame r 0 raster_structure4 address: 011h 15-11 C not used. C C 10-0 raster_structure_4[10:0] active lines per field r 0 table 4-4: host interface descript ion for raster structure registers register name bit name description r/w default table 4-5: supported video standards vd_std[4:0] smpte standard video format length of hanc length of active video to t a l samples smpte352m lines 00h 296m (hd) 1280x720/60 (1:1) 358 1280 1650 13 01h 296m (hd) 1280x720/60 (1:1) - em 198 1440 1650 13 02h 296m (hd) 1280x720/30 (1:1) 2008 1280 3300 13 03h 296m (hd) 1280x720/30 (1:1) - em 408 2880 3300 13 04h 296m (hd) 1280x720/50 (1:1) 688 1280 1980 13 05h 296m (hd) 1280x720/50 (1:1) - em 240 1728 1980 13 06h 296m (hd) 1280x720/25 (1:1) 2668 1280 3960 13 07h 296m (hd) 1280x720/25 (1:1) - em 492 3456 3960 13 08h 296m (hd) 1280x720/24 (1:1) 2833 1280 4125 13 09h 296m (hd) 1280x720/24 (1:1) - em 513 3600 4125 13 0ah 274m (hd) 1920x1080/60 (2:1) or 1920x1080/30 (psf) 268 1920 2200 10, 572 0bh 274m (hd) 1920x1080/30 (1:1) 268 1920 2200 18 0ch 274m (hd) 1920x1080/50 (2:1) or 1920x1080/25 (psf) 708 1920 2640 10, 572 0dh 274m (hd) 1920x1080/25 (1:1) 708 1920 2640 18
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 39 of 64 4.8.4 packet generation and insertion the GS1572 can calculate, asse mble and insert trs id wo rds and various types of ancillary data packets. these features are only available when the ioproc_en/dis pin is set high. individual insertion features may be enabled or disabled via the ioproc_disable register ( table 4-6 ). all of the ioproc_disable register bits default to 'zero' after device reset, enabling all of the processing features. to disable any individual error correction feature, set the corresponding bit high in this register. 0eh 274m (hd) 1920x1080/25 (1:1) - em 324 2304 2640 18 0fh 274m (hd) 1920x1080/25 (psf) - em 324 2304 2640 10, 572 10h 274m (hd) 1920x1080/24 (1:1) 818 1920 2750 18 11h 274m (hd) 1920x1080/24 (psf) 818 1920 2750 10, 572 12h 274m (hd) 1920x1080/24 (1:1) - em 338 2400 2750 18 13h 274m (hd) 1920x1080/24 (psf) - em 338 2400 2750 10, 572 14h 295m (hd) 1920x1080/50 (2:1) 444 1920 2376 10, 572 15h 260m (hd) 1920x1035/60 (2:1) 268 1920 2200 10, 572 16h 125m (sd) 1440x487/60 (2:1) (or dual link progressive) 268 1440 1716 13, 276 17h 125m (sd) 1440x507/60 (2:1) 268 1440 1716 13, 276 19h 125m (sd) 525-line 487 generic C C 1716 13, 276 1bh 125m (sd) 525-line 507 generic C C 1716 13, 276 18h itu-r bt.656 (sd) 1440x576/50 (2:1) (or dual link progressive) 280 1440 1728 9, 322 1ah itu-r bt.656 (sd) 625-line generic (em) C C 1728 9, 322 1dh unknown hd C C C C C 1eh unknown sd C C C C C 1ch, 1fh reserved C C C C C note: though the GS1572 will work correctly on and serialize both 59.94hz and 60hz formats, it will not distinguish between the m. table 4-5: supported video standards (continued) vd_std[4:0] smpte standard video format length of hanc length of active video to t a l samples smpte352m lines
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 40 of 64 4.8.4.1 smpte 352m payload identifier packet insertion the GS1572 can generate and insert smpte 352m payloa d identifier ancillary data packets. when this feature is enabled, the device will automatically generate the ancillary data preambles, (did, sdid, dbn, dc), and calculate the chec ksum. the smpte 352m packet table 4-6: host interface description for internal processing disable register register name bit name description r/w default ioproc_disable address: 000h 15-13 C not used. set to zero. C 0 12 C setting this bit low allows the timing mode to be selectable through the cea_861 bit. setting this bit high allows the timing mode to be selectable through the cea_861 bit, regardless of the pin setting. C0 11 anc_ins enable or disable ancillary data insertion. set low for enable. set high for disable. r/w 0 10 C not used. set to zero. C 0 9 cea_861 cea_861 pin override bit. active when tim_861_pin_en bit is set high. set cea_861 bit low to enable cea 861 timing. set this bit high to disable cea 861 timing. r/w 0 8 h_config horizontal blanking timing configuration. set low when the h/hsync input timing is based on active line blanking (default). set high when the h input timing is based on the h bit of the trs words. see figure 4-2 . r/w 0 7 C not used. set to zero. C 0 6 352m_ins smpte352m packet insertion. in hd mode, 352m packets are inserted in the luma channel only when one of the bytes in the video_format_a or video_format_b registers are programmed with non-zero values. set high to disable. r/w 0 5 illegal_remap illegal code remapping. detection and correction of illegal code words within the active picture area (ap). set high to disable. r/w 0 4 edh_crc_ins error detection & handling (edh) cyclical redundancy check (crc) error correction. in sd mode the GS1572 will generate and insert edh packets. set high to disable. r/w 0 3 anc_csum_ins ancillary data checksum insertion. set high to disable. r/w 0 2 crc_ins luma and chroma line-based crc insertion. in hd mode, line-based crc words are inserted in both the luma and chroma channels. set high to disable r/w 0 1 lnum_ins luma and chroma line number insertion - hd mode only. set high to disable. r/w 0 0 trs_ins timing reference signal insertion. set high to disable. r/w 0
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 41 of 64 will be inserted into the data stream according to the line numbers programmed in the line_352m_f1 and line_352m_f2 registers ( table 4-7 ). packet insertion will only take place if at least one of the bytes in the video_format_a or video_format_b registers are programmed with a non-zero value ( table 4-8 ). in addition, the 352m_ins bit must be set low ( table 4-6 ). the GS1572 will differentiate be tween psf and interlaced fo rmats based on bits 14 and 15 of the video_fo rmat_a register. the packets will be inserted immediately after the eav word in sd video streams and immediately after the line-based crc word in the luma channel of hd video streams. if other ancillary packets exist in the horizontal ancillary space 352m packets will be inserted immediately following these packet s. smpte 352m packets will not be inserted if there is insufficient room in the hanc space. note: if there are existing 352m packet s in the input stream, and anc_blank is set high (disabled), then the ex isting data is pr eserved and new 352m is inserted. GS1572 does not overwrite existing 352m data. table 4-7: host interface description for smpte 352m packet line number insertion registers register name bit name description r/w default line_0_352m address: 01bh 15-11 C not used. C C 10-0 line_0_352m[10:0] line number where smpte352m packet is inserted in field 1. r/w 0 line_1_352m address: 01ch 15-11 C not used. C C 10-0 line_1_352m[10:0] line number where smpte352m packet is inserted in field 2. r/w 0 table 4-8: host interface description for smpte 352m payload identifier registers register name bit name description r/w default video_format_b address: 00bh 15-8 video_format[2] [7:0] smpte352m byte 4 information must be programmed in this register when 352m_ins = low. r/w 0 7-0 video_format[1] [7:0] smpte352m byte 3information must be programmed in this register when 352m_ins = low. r/w 0 video_format_a address: 00ah 15-8 video_format[4] [7:0] smpte352m byte 2information must be programmed in this register when 352m_ins = low. r/w 0 7-0 video_format[3] [7:0] smpte352m byte 1information must be programmed in this register when 352m_ins = low. r/w 0
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 42 of 64 4.8.4.2 illegal code remapping if the illegal_remap bit of the ioproc_disable register is set low, the GS1572 will remap all codes within the active picture betw een the values of 3fch and 3ffh to 3fbh. all codes within the ac tive picture area between the va lues of 000h and 003h will be remapped to 004h. in addition, 8-bit trs and ancillary data preambles will be remapped to 10-bit values. 4.8.4.3 edh generation and insertion when operating in sd mode, (sd/hd = high), the GS1572 will generate and insert complete edh packets. packet generation and insertion will only take place if the edh_crc_ins bit of the ioproc_d isable register is set low. the GS1572 will generate all of the required edh packet data, including all ancillary data preambles did, dbn, dc , reserved code words, and the checksum. calculation of both full field (ff) and active picture (ap) crc's will be carried out by the device. smpte rp165 specifies the calculation ranges and scope of edh da ta for standard 525 and 625 component digital interfaces. the GS1572 uses these standard ranges by default. if the received video format does not correspond to 525 or 625 digital component video standards, then the ranges will be determ ined from the received trs id words or supplied h_blanking, v_blanking, and f_digital timing signals; or hsync, vsync and de cea 861 timing signals. see ?hvf timing? on page 26, and ?cea 861 timing? on page 28, . the first active and full field pixel will alwa ys be the first pixel after the sav trs code word. the last active and full field pixel will always be the last pixel before the start of the eav trs code words. edh error flags (edh, eda, idh, ida and ues) for ancillary data, full field and active picture will also be inserted when the corres ponding bit of the edh_flag register is set high. ( table 4-9 ). note 1: the edh flag registers must be updated once per field. the prepared edh packet will be inserted at the appropriate line according to smpte rp165. the start pixel position of the inserted packet will be based on the sav position of that line such that the last byte of the edh packet (the checksum) will be placed in the sample immediately preceding the start of the sav trs word. note 2: edh packets will not be inserted if there is insufficient room in the hanc space.
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 43 of 64 4.8.4.4 ancillary data checksum generation and insertion the GS1572 will calculate checks ums for all detected ancill ary data packets presented to the device. these calculated checksum values are inserted into the data stream prior to serialization. ancillary data checksum generation and insertion will only take place if the anc_csum_ins bit of the ioproc _disable register is set low. note: the GS1572 will recalculate the checksum and, if incorrect, will re-insert the correct value. however, the GS1572 does not check the correctness of the parity bit. that is, if all the bits from 0 to 8 in the checksum word are correct and on ly bit 9 (the parity table 4-9: host interface description for edh flag register (sd mode only) register name bit name description r/w default edh_flag address: 002h 15 C not used. C C 14 anc-ues ancillary unknown error status flag will be generated and inserted. r/w 0 13 anc-ida ancillary internal device error detected already flag will be generated and inserted. r/w 0 12 anc-idh ancillary internal device error detected here flag will be generated and inserted. r/w 0 11 anc-eda ancillary error detected already flag will be generated and inserted. r/w 0 10 anc-edh ancillary error detected here flag will be generated and inserted. r/w 0 9 ff-ues full field unknown error flag will be generated and inserted. r/w 0 8 ff-ida full field internal device error detected already flag will be generated and inserted. r/w 0 7 ff-idh full field internal de vice error detected flag will be generated and inserted. r/w 0 6 ff-eda full field error detected already flag will be generated and inserted. r/w 0 5 ff-edh full field error detected here flag will be generated and inserted. r/w 0 4 ap-ues active picture unknown error status flag will be generated and inserted. r/w 0 3 ap-ida active picture internal device error detected already flag will be generated and inserted. r/w 0 2 ap-idh active picture internal device error detected here flag will be generated and inserted. r/w 0 1 ap-eda active picture error detected already flag will be generated and inserted. r/w 0 0 ap-edh active picture error detected here flag will be generated and inserted. r/w 0
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 44 of 64 bit, which is the inverse of bit 8) is incorrect, then the checksum word is not re-calculated. if even one of bit 0 to bit 8 has an incorrect value, then the checksum word is re-calculated and re-inserted. 4.8.4.5 line based crc generation and insertion the GS1572 will generate and insert line based crc wo rds into both the luma and chroma channels of the data stream. this fe ature is only available in hd mode and is enabled by setting the crc_ins bit of the ioproc_disable register low. 4.8.4.6 hd line number generation and insertion in hd mode, the GS1572 will ca lculate and insert line nu mbers into the luma and chroma channels of the output data stream. line number generation is in accordance with the relevant hd video standard as determined by the device, see automatic video standard detection on page 37 . this feature is enabled when sd/hd = low, and the lnum_ins bit of the ioproc_disable regi ster is set low. 4.8.4.7 trs generation and insertion the GS1572 can generate and insert 10-bi t trs code words into the data stream as required. this feature is enabled by sett ing the trs_ins bit of the ioproc_disable register low. trs word generation will be performed in accordance with the timing parameters extracted from either the received trs id words, the supplied h_blanking, v_blanking, and f_digital timing signals, or the cea 861 timing signals, see hvf timing on page 26 and cea 861 timing on page 28 . 4.9 parallel to serial conversion the GS1572 can accept either 10- bit or 20-bit parallel data in both sd and hd modes. the supplied pclk rate must correspond to the settings of the sd/hd and 20bit/10bit pins as shown in table 4-10 . table 4-10: serial digital output rates supplied pclk rate serial digital output rate pin settings sd/hd 20bit/10bit 74.25 or 74.25/1.001mhz 1.485 or 1.485/1.001gb/s low high 148.5 or 148.5/1.001mhz 1.485 or 1.485/1.001gb/s low low 13.5mhz 270mb/s high high 27mhz 270mb/s high low
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 45 of 64 4.10 internal clockcleaner ? pll to obtain a clean clock signal for serializat ion and transmission, an external vco signal is locked to the input pclk via the GS1572's integrated phase-lock ed loop. this high quality analog pll has a bang-bang implementation, which automatically narrows the loop bandwidth in the presence of jitter, allowing the GS1572 to signific antly attenuate jitter on the incoming pclk. 4.10.1 external vco the GS1572 requires the go1555 external voltage co ntrolled oscillator as part of its internal pll. power for the external vco is generated by the GS1572 fr om an integrated voltage regulator. the internal regulator uses +3.3 v supplied on the cp_vdd/cp_gnd pins to provide +2.5v on the vco_vcc/vco_gnd pins. the external vco produces a 1.485ghz signal for the pll, input on the vco pin of the device. see typical application circuit on page 59 . note: the vco_vcc output voltage is guaran teed to be 2.5v only when supplying power to the go1555. the vco_vcc pin should not be shorted to gnd under any circumstances. 4.10.2 loop filter the GS1572 pll loop filter is an external first order filt er formed by a series rc connection as shown in the typical application circuit on page 59 . the loop filter resistor value sets the bandwidth of the pll and the capacitor value controls its stability and lock time. a loop filter resistor value between 1 to 20 and a loop fi lter capacitor value between 1 f to 33 f are recommended. the GS1572 uses a non-linear, bang-bang, pll, therefore its bandwi dth scales with the input jitter amplitude - greater input jitter results in a smaller lo op bandwidth causing more of the input jitter to be rejected. for a given input jitter amplitude, a smaller loop filter resistor produces a narrower loop ba ndwidth. with an input jitter amplitude of 300ps, for example, the pll bandwidth can be adjusted from 2khz to 40khz by varying the loop filter resistor, as shown in table 4-11: loop filter component values . for use with gen-clocks ? timing generators, a narrow loop bandwidth is recommended. increasing the loop filter capacitor value increases the stability of the pll, but results in a longer lock time. for loop filter resistors smaller than 7 , a capacitor value of 33 f is recommended, while larger resistor values can accommodate smaller capacitors. sample combinations of the loop filter resistor and ca pacitor values are shown in table 4-11: loop filter component values , along with the resulting loop bandwidth. additional loop bandwidths ca n be achieved by using diffe rent loop filt er resistor values.
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 46 of 64 4.10.3 lock detect output the locked output will be asserted high when the internal pll has locked to the input pclk signal. in the absence of the pclk, when frequency lock has not been achieved, and during device reset, th e locked output will be low. lock time, the time it takes for the internal pll to frequency-lock to the reference pclk following power-up or standby, is determined by the loop filter capacitor value chosen. a 1 f loop filter capacitor, for example, wi ll result in lock ti mes of less than 500 s. a 33 f loop filter capacitor, on the other hand, will result in a lock time of greater than 5s. note 1: when the pll is in the process of locking to the reference pclk, the locked pin may generate low and high pulses. the durations of these pulses are dependent on the loop filter capacitor value, but do not exceed 30ms. once the pll has achieved frequency lock, the locked pin will remain high and not change state. note 2: when the GS1572 is placed in standby mode, the value of locked is maintained although the pll does lose lock to the reference pclk. when standby is released, the pll will re-lock. during this time, if the locked pin was previously high, it will de-assert approximately 6 s later, and re-assert once the pll has re-locked to the input pclk. 4.11 serial digital output the GS1572 includes a smpte co mpliant current mode differe ntial serial digital cable driver with automatic slew rate control. the serial output has improved eye quality, exceptional orl performance, and reduced duty cycle distortion. the cable driver uses a separate +3.3v dc power supply provided via the cd_vdd and cd_gnd pins. to enable the output, sdo_en/dis must be set high. setting the sdo_en/dis signal low will set the sdo and sdo output pins to high-impedance, resulting in reduced device power consumption. table 4-11: loop filter component values loop filter resistor value typical loop bandwidth* recommended loop filter capacitor value comments 1 2khz 33 f narrow bandwidth - provides maximum jitter reduction. long lock-time. 7 8khz 10 f 20 40khz 1 f wide bandwidth. fast lock-time. * measured with 300ps pk-pk input jitter on pclk
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 47 of 64 4.11.1 output swing nominally, the voltage swing of the serial digital output is 800mvp-p single-ended into a 75 load. this is set externally by connecting the rset pin to cd_vdd through a 750 1% resistor . 4.12 gspi host interface the GS1572 host interface, also called the gennum serial pe ripheral interface (gspi), provides access to configuration/status registers for the video processing functions of the chip. by default, the device will be ?live at power up?, with all major functional blocks active in the defined default operating conditions described below. dedicated configuration pins are provided for basic configuration of the device. the host interface is provided to allow optional configuration of some of the more advanced functions and operating modes of the device. to simplify host interface access to the configuration and status registers, a single contiguous register map is provided for the video functions. registers are grouped by like function and wherever possible functional configuration will not be spread acro ss multiple registers. the gspi is comprised of a serial data inpu t signal (sdin), serial data output signal (sdout), an active low chip select (cs ), and a burst clock (sclk). the burst clock must have a duty cycle between 40% and 60% while active. because these pins are shared with the jtag interface port, an additional control signal pin jtag/host is provided. when jtag/host is low, the gspi interface is enabled. when operating in gspi mode, the sclk, sdin, and cs are inputs to the device. the sdout loops the sdin back out when th e gspi is in write mode, or when cs is high, allowing multiple devices to be connected in series. during reset, sdout is held in high-impedance mode. the interface is illustrated in the figure 4-10 . each gspi access begins with a 16-bit command word on sdin indicating the address of the register of interest. this is followed by a 16-bit data word on sdin in write mode, or a 16-bit data word on sdout in read mode. note 1: when the device is in standby mode (standby = high) no host interface register can be read back or written to. attempting a read or write will not damage the device. however, all re ads will return a value of zero, an d no writes will take effect. note 2: in the configuration and status registers, there are several registers that have been designated as reserved. if possible, writ ing to these registers should be avoided. if writing a value to these registers is not avoidable, then only a value of ?zero? should be written to these registers. writing a value of ?one? may alter the functional behaviour of GS1572, but will not permanently damage the device.
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 48 of 64 figure 4-10: gennum serial peripheral interface (gspi) 4.12.1 command word description the command word consists of a 16-bit word transmitted msb first and contains a read/write bit, an auto-increment bit and a 12-bit address. figure 4-11 shows the command word format and bit configuratio ns. command words are clocked into the GS1572 on the rising edge of the serial cloc k sclk, which operates in a burst fashion. when the auto-increment bit is set low, each command word must be followed by only one data word to ensure proper operation. if the auto-increment bit is set high, the following data word will be written into the address specified in the command word, and subsequent data words will be written into incremental addresses from the previous data word. this facilitates mu ltiple address writes without sending a command word for each data word. note: all registers can be written to through single address access or through the auto-increment feature. however, the lsb of the video registers cannot be read through single address read-back. single address read -back will return a ?zero? value for the lsb. if auto-increment is used to read back the values from at least two registers, the lsb value read will always be correct. therefore, for register read-back, it is recommended that auto-increment be used and that at least two registers be read back at a time. figure 4-11: command word figure 4-12: data word appli c ation host sc lk sc lk sc lk cs 1 s dout s din s dout s dout cs s din s din cs 2 gs 1572 gs 1572 cs s b l s b a4 a5 a 6 a8 a7 a9 a3 a2 a1 a0 a10 a11 autoin c r s v r s v r/w r s v = reserve d . must b e set to zero. r/w: rea d c omman d when r/w = 1 write c omman d when r/w = 0 m s b l s b d4 d5 d 6 d8 d7 d9 d3 d2 d1 d0 d10 d11 d12 d13 d14 d15
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 49 of 64 4.12.2 data read and write timing read and write mode timing for the gspi interface is shown in figure 4-13 and figure 4-14 respectively. the timing parameters are defined in table 4-12 . when several devices are connected to the gspi chain, only one cs must be set low during a read sequence. during the write sequence, all command and subsequent data words are looped through from sdin to sdout. when several devices are connected to the gspi chain, data can be written simultaneously to all the devices that have cs set low. figure 4-13: gspi read mode timing table 4-12: gspi timing parameters parameter definition specification t 0 the minimum duration of time chip select, cs , must be low before the first sclk rising edge. 1.5 ns t 1 the minimum sclk period. 100 ns t 2 duty cycle tolerated by sclk. 40% to 60% t 3 minimum input se tup time. 1.5 ns t 4 write cycle: the minimum du ration of time between the last sclk command (or data word if the auto-increment bit is high) and the first sclk of the data word. 37.1 ns t 5 read cycle: the minimum duration of time between the last sclk command (or data word if the auto-increment bit is high) and the first sclk of the data word. 148.4 ns t 6 minimum output hold time. 1.5 ns t 7 the minimum duration of ti me between the last sclk of the gspi transaction and when cs can be set high. 37.1 ns t 8 minimum input hold time. 1.5 ns sc lk cs s din s dout t 5 t 6 r/w r s v r s v autoin c a11 a10 a9 a8 a7 a 6 a5 a4 a3 a2 a1 a0 r/w r s v r s v autoin c a11 a10 a9 a8 a7 a 6 a5 a4 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d 6 d5 d4 d3 d2 d1 d0
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 50 of 64 figure 4-14: gspi write mode timing 4.12.3 configuration and status registers table 4-13 summarizes the GS1572's internal status and co nfiguration registers. table 4-14 summarizes the video core stat us and configuration registers. all bits are available to the host via the gspi. r/w r s vr s v auto _in c a0 a1 a2 a3 a4 a5 a 6 a7 a8 a9 a11 a10 d15 d14 d13 d12 d0 d1 d2 d3 d4 d5 d 6 d7 d8 d9 d11 d10 sc lk cs s din s dout t 0 t 3 t 1 t 2 r/w r s vr s v auto _in c a0 a1 a2 a3 a4 a5 a 6 a7 a8 a9 a11 a10 d15 d14 d13 d12 d0 d1 d2 d3 d4 d5 d 6 d7 d8 d9 d11 d10 t 8 t 4 t 7 table 4-13: GS1572 internal registers address register name see section 000h ioproc_disable section 4.8.4 002h edh_flag section 4.8.4.3 004h video_standard section 4.8.2 005h - 009h anc_data_type ? 00ah - 00bh video_format section 4.8.4.1 00eh - 011h raster_structure section 4.8.2 01ah global_error_mask_vector ? 01bh - 01ch line_352m section 4.8.4.1
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 51 of 64 4.12.3.1 configuration and status registers table 4-14: configuration and status registers address register name bit description r/w default 000h reserved 15-13 reserved. r 000b tim_861_pin_en 12 selects pin for control for 861 timing converter. reference: section 4.3.2 on page 28 . r/w 0 anc_ins 11 disable for ancillary data insertion feature. reference: section 4.7 on page 34 . r/w 0 reserved 10 reserved. r 0 cea_861 9 disable 861 timing converter. reference: section 4.3.2 on page 28 . r/w 0 h_config 8 horizontal sync timing input configuration. set low when the h input timing is based on active line blanking (default). set high when the h input timing is based on the h bit of the trs words. reference: section 4.3.1 on page 26 . r/w 0 reserved 7 reserved. r 0 352m_ins 6 smpte352m packet insertion. in hd mode, 352m packets are inserted in the luma channel only when one of the bytes in the video_format_a or video_format_b registers are programmed with non-zero values. set high to disable. reference: section 4.8.4.1 on page 40 . r/w 0 illegal_remap 5 illegal code remapping. detection and correction of illegal code words within the active picture area (ap). set high to disable. reference: section 4.8.4.2 on page 42 . r/w 0 edh_crc_ins 4 error detection & handling (edh) cyclical redundancy check (crc) error correction. in sd mode the GS1572 will generate and insert edh packets. set high to disable. reference: section 4.8.4.3 on page 42 . r/w 0 anc_csum_ins 3 ancillary data checksum insertion. set high to disable. reference: section 4.8.4.4 on page 43 . r/w 0 crc_ins 2 luma and chroma line-based crc insertion. in hd mode, line-based crc words are inserted in both the luma and chroma channels. set high to disable reference: section 4.8.4.5 on page 44 . r/w 0 lnum_ins 1 luma and chroma line number insertion - hd mode only. set high to disable. reference: section 4.8.4.6 on page 44 . r/w 0 trs_ins 0 timing reference signal insertion. set high to disable. reference: section 4.8.4.7 on page 44. r/w 0
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 52 of 64 001h reserved 15-0 reserved. r n/a 002h reserved 15 reserved. r/w 0 anc-ues 14 ancillary unknown error status flag will be generated and inserted. sd mode only. reference: section 4.8.4.3 on page 42. r/w 0 anc-ida 13 ancillary internal device error detected already flag will be generated and inserted. sd mode only. reference: section 4.8.4.3 on page 42. r/w anc-idh 12 ancillary internal device error detected here flag will be generated and inserted. sd mode only. reference: section 4.8.4.3 on page 42. r/w 0 anc-eda 11 ancillary error detected already flag will be generated and inserted. sd mode only. reference: section 4.8.4.3 on page 42. r/w 0 anc-edh 10 ancillary error detected here flag will be generated and inserted. sd mode only. reference: section 4.8.4.3 on page 42. r/w 0 ff-ues 9 full field unknown error flag will be generated and inserted. sd mode only. reference: section 4.8.4.3 on page 42. r/w 0 ff-ida 8 full field internal device error detected already flag will be generated and inserted. sd mode only. reference: section 4.8.4.3 on page 42. r/w 0 ff-idh 7 full field internal device error detected flag will be generated and inserted. sd mode only. reference: section 4.8.4.3 on page 42. r/w 0 ff-eda 6 full field error detected already flag will be generated and inserted. sd mode only. reference: section 4.8.4.3 on page 42. r/w 0 ff-edh 5 full field error detected here flag will be generated and inserted. sd mode only. reference: section 4.8.4.3 on page 42. r/w 0 ap-ues 4 active picture unknown error status flag will be generated and inserted. sd mode only. r/w 0 ap-ida 3 active picture internal device error detected already flag will be generated and inserted. sd mode only. r/w 0 ap-idh 2 active picture internal de vice error detected here flag will be generated and inserted. sd mode only. r/w 0 ap-eda 1 active picture error detected already flag will be generated and inserted. sd mode only. r/w 0 ap-edh 0 active picture error detected here flag will be generated and inserted. sd mode only. r/w 0 table 4-14: configuration and status registers (continued) address register name bit description r/w default
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 53 of 64 003h reserved 15-0 reserved. r n/a 004h reserved 15 reserved r 0 vid_std[4:0] 14-10 reports the detected video standard. reference: section 4.8.3 on page 38 . r 00000b int_prog 9 interlace/progressive: set low if detected video standard is progressive and is set high if it is interlaced. reference: section 4.8.3 on page 38 . r0 std_lock 8 standard lock: set high when the device has achieved full synchronization. reference: section 4.8.3 on page 38 . r0 reserved 7-0 reserved. r n/a 005h-009h reserved 15-0 reserved. r n/a 00ah video_format_a[15:8] 15-8 smpte 352m by te 2 information must be programmed in this register when 352m_ins = low. reference: section 4.8.4.1 on page 40 . r/w 0 video_format_a[7:0] 7-0 smpte 352m byte 1 information must be programmed in this register when 352m_ins = low. reference: section 4.8.4.1 on page 40 . r/w 0 00bh video_format_b[15:8] 15-8 smpte 352m by te 4 information must be programmed in this register when 352m_ins = low. reference: section 4.8.4.1 on page 40 . r/w 0 video_format_b[7:0] 7-0 smpte 352m byte 3 information must be programmed in this register when 352m_ins = low. reference: section 4.8.4.1 on page 40 . r/w 0 00ch-00dh reserved 15-0 reserved. r n/a 00eh reserved 15-12 reserved. C C raster_structure_1 11-0 words per active line reference: section 4.8.2 on page 37 . r0 00fh reserved 15-13 reserved. C C raster_structure_2 12-0 words per total line. reference: section 4.8.2 on page 37 . r0 010h reserved 15-11 reserved. C C raster_structure_3 10-0 total lines per frame reference: section 4.8.2 on page 37 . r0 011h reserved 15-11 reserved. C C raster_structure_4 10-0 active lines per field reference: section 4.8.2 on page 37 . r0 012h reserved 15-0 reserved. C 0 table 4-14: configuration and status registers (continued) address register name bit description r/w default
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 54 of 64 013h reserved 15-0 reserved. C C 014h reserved 15-0 reserved. C C 015h reserved 15-0 reserved. C C 016h reserved 15-0 reserved. C C 017h reserved 15-0 reserved. C C 018h reserved 15-0 reserved. C C 019h reserved 15-0 reserved. C C 01ah reserved 15-0 reserved. r n/a 01bh reserved 15-11 reserved. C C line_0_352m[10:0] 10-0 line number wher e smpte352m packet is inserted in field 1. reference: section 4.8.4.1 on page 40 . r/w 0 01ch reserved 15-11 reserved. C C line_1_352m[10:0] 10-0 line number wher e smpte352m packet is inserted in field 2. reference: section 4.8.4.1 on page 40 . r/w 0 01dh-01eh reserved 15-0 reserved. r n/a 01fh format_err 15 861 timing format error flag. r 0 reserved 14-9 reserved. r 0 line_offset 8-6 shifts the timing of th e output 861 timing signal by up to +/-3 lines. r/w 0 pixel_offset 5-3 shifts the timing of th e output 861 timing signal by up to +/-3 pixels. r/w 0 reserved 2-1 reserved. r 0 fsync_invert 0 inverts the polarity of the detected field. r/w 0 020h anc_ins_mode 15 selects the anc data insertion operating mode. 0 separate line mode 1 concatenated mode reference: section 4.7.1 on page 35 . r/w 0 packet_missed 14 flag to indicate ancillary data packet could not be inserted in its entirety. reference: section on page 34 . r0 rw_conflict 13 flag to indicate the same ram address was read and written at the same time. r0 reserved 12-11 reserved r/w 0000b first_line_number 10-0 defines the line number for the first line in separate line mode or the single line for concatenated mode. r/w 0 table 4-14: configuration and status registers (continued) address register name bit description r/w default
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 55 of 64 021h anc_type 15 selects the anc data type as hanc or vanc. 0 hanc 1 vanc reference: section 4.7.2 & section 4.7.3 r/w 0 stream_type 14 selects the luma or chroma stream for anc insertion. 0 luma stream 1 chroma stream this field is ignored in sd mode. reference: section 4.7.2 & section 4.7.3 r/w 0 reserved 13-10 reserved r/w 0000b first_line_number_of_ words 9-0 defines the total number of data words to insert on the first line in separate line mode or single line in the concatenated mode. r/w 0 022h reserved 15-11 reserved r/w 00000b second_line_number 10-0 defines the line nu mber for anc data insertion for the 2nd line in separate line mode. r/w 0 023h anc_type 15 selects the anc data type as hanc or vanc. 0 hanc 1 vanc reference: section 4.7.2 & section 4.7.3 r/w 0 stream_type 14 selects the luma or chroma stream for anc insertion. 0 luma stream 1 chroma stream this field is ignored in sd mode. reference: section 4.7.2 & section 4.7.3 r/w 0 reserved 13-10 reserved r/w 0000b second_line_number_o f_words 9-0 defines the total number of data words to insert on the 2nd line in separate line mode. r/w 0 024h reserved 15-11 reserved r/w 00000b third_line_number 10-0 defines the line nu mber for anc data insertion for the 3rd line in separate line mode. r/w 0 025h anc_type 15 selects the anc data type as hanc or vanc. 0 hanc 1 vanc reference: section 4.7.2 & section 4.7.3 r/w 0 stream_type 14 selects the luma or chroma stream for anc insertion. 0 luma stream 1 chroma stream this field is ignored in sd mode. reference: section 4.7.2 & section 4.7.3 r/w 0 reserved 13-10 reserved. r/w 0000b third_line_number_of_ words 9-0 defines the total number of data words to insert on the 3rd line in separate line mode. r/w 0 table 4-14: configuration and status registers (continued) address register name bit description r/w default
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 56 of 64 4.13 jtag test operation when the jtag/host input pin of the GS1572 is set high, the host interface port will be configured for jtag test operation. in this mode, pins j9, j10, k9, and k10 become tdo, tck, tms, and tdi. in addition, the reset_trst pin will operate as the test reset pin. boundary scan testing usin g the jtag interface will be enabled in this mode. there are two ways in which jtag can be used on the GS1572: 1. as a stand-alone jtag interface to be used at in-circuit ate (automatic test equipment) during pcb assembly; or 2. under control of a host processor for appl ications such as sy stem power on self tests. when the jtag tests are applied by ate, care must be taken to disable any other devices driving the digital i/o pins. if the tests are to be applied only at ate, this can be 026 reserved 15-11 reserved r/w 00000b fourth_line_number 10-0 defines the line number for anc data insertion for the 4th line in separate line mode. r/w 0 027h anc_type 15 selects the anc data type as hanc or vanc. 0 hanc 1 vanc reference: section 4.7.2 & section 4.7.3 r/w 0 stream_type 14 selects the luma or chroma stream for anc insertion. 0 luma stream 1 chroma stream this field is ignored in sd mode. reference: section 4.7.2 & section 4.7.3 r/w 0 reserved 13-10 reserved r/w 0000b fourth_line_number_o f_words 9-0 defines the total number of data words to insert on the 4th line in separate line mode. r/w 0 040h-07fh anc_data_bank1 15-0 first bank of user defined 8 bit words. 15-8: high order byte 7-0: low order byte w0 080h-0bfh anc_data_bank2 15-0 second bank of user defined 8 bit words. 15-8: high order byte 7-0: low order byte w0 0c0h-0ffh anc_data_bank3 15-0 third bank of user defined 8 bit words. 15-8: high order byte 7-0: low order byte w0 100h-13fh anc_data_bank4 15-0 fourth bank of user defined 8 bit words. 15-8: high order byte 7-0: low order byte w0 table 4-14: configuration and status registers (continued) address register name bit description r/w default
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 57 of 64 accomplished with tri-state buffers used in conjunction with the jtag/host input signal. this is shown in figure 4-15 . figure 4-15: in-circuit jtag alternatively, if the test capabilities are to be used in the system, the host processor may still control the jtag/host input signal, but some means for tri-stating the host must exist in order to use the interface at ate. this is represented in figure 4-16 . figure 4-16: system jtag note: scan coverage is limited to digital pins only. there is no scan coverage for analog pins vco, sdo/sdo , rset, lf, and cp_res. note: the sd/hd pin must be held low during scan and therefore has no scan coverage. please contact your gennum representative to obtain the bsdl model for the GS1572. appli c ation ho s t gs 1572 cs _tm s sc lk_t c k s din_tdi s dout_tdo j ta g _ho s t in- c ir c uit ate pro b e appli c ation ho s t gs 1572 cs _tm s sc lk_t c k s din_tdi s dout_tdo j ta g _ho s t in- c ir c uit ate pro b e tri- s tate
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 58 of 64 4.14 device reset in order to initialize all internal operating conditions to their default states, hold the reset_trst signal low for a minimum of t reset = 10ms after all power supplies are stable. there are no requirements for power supply sequencing. when held in reset, all device outputs will be driven to a high-impedance state. figure 4-17: reset pulse supply voltage reset_trst t reset 95% of nominal level nominal level reset reset t reset
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 59 of 64 5. application reference design 5.1 typical application circuit h v s dout_tdo csb _tm s f data_in14 p c lk c d_vdd_ s wit c hed sc lk_t c k s din_tdi data_in15 s do- s do+ data_in1 6 data_in17 data_in18 data_in19 data_in0 data_in1 data_in2 data_in3 data_in4 data_in5 data_in 6 data_in7 data_in[19..0] data_in8 data_in9 data_in10 data_in11 data_in12 data_in13 s tandby_inv c d_vdd_ s wit c hed s tandby_inv lo c ked s tandby p c lk s do s don re s et_tr s t b sc lk_t c k s din_tdi csb _tm s s dout_tdo f v h data_in[19:0] s mpte_bypa ssb s d/hd b dvb_a s i j ta g /ho s t b an c _blank b 20 b it/10 b it b s do_en/di sb dete c t_tr s iopro c _en/di sb s tandby tim_8 6 1 lo c ked +1.8v g nd g nd v c o_v cc g nd +3.3v_ c d v c o_v cc +3.3v_ c d +3.3v +1.8v g nd g nd +1.8v io_vdd io_vdd io_vdd g nd_a g nd_a g nd_a g nd_a v c o_ g nd v c o_ g nd v c o_ g nd v c o_ g nd v c o_ g nd v c o_ g nd v c o_ g nd g nd g nd +3.3v_ c d +3.3v io_vdd +3.3v g nd g nd note: v c o_v cc an d v c o_ g nd are the outputs from an internal volta g e re g ulator. they supply power to the g o1555 external v c o. r an d l form the output return loss c ompensation network. s ub j e c t to c han g e pla c e c lo s e to gs 1572. i s olate with a moat on all layer s . pla c e a s c lo s e a s po ss ible to the pin s of the gs 1572. 2.5v internal i s olated power c ore_vdd, io_vdd de c ouplin g optional termination s optional c able driver power down s wit c h (for u s e in s tandby mode) c 80 10nf c 80 10nf 1a 1 1y 2 2a 3 2y 4 3a 5 3y 6 g nd 7 4y 8 4a 9 5y 10 5a 11 6 y 12 6 a 13 v cc 14 u22 74lv c 04/ s o u22 74lv c 04/ s o 1 2 c 72 4u7 c6 7 10nf c6 7 10nf 1 2 c 75 4u7 c 75 4u7 r 6 1 750r0 r 6 1 750r0 c66 10nf c66 10nf 2 1 d1 led d1 led r r 1 2 c c c6 2 10nf c6 2 10nf r 6 4 75r c6 4 np c6 4 np vin 3 out 1 en 4 g nd 5 g nd 2 u17 mi c 940 6 0 u17 mi c 940 6 0 r 6 8 (np) r 6 8 (np) c 83 10nf c 83 10nf r5 6 3r3 r5 6 3r3 c 70 10nf c 73 10nf c 73 10nf l1 5n 6 1 2 c6 81u r 6 2 75r c 81 10nf c 81 10nf r 66 22k r 6 0 75r (np) c 77 (np) r5 500r r5 500r 1 2 c6 31u c6 31u c 87 10nf c 87 10nf r71 1k r71 1k l2 5n 6 1 2 c6 9 33u c6 9 33u r 6 5 75r c p_re s b7 v c o_v cc a8 v c o_ g nd b8 c ore_ g nd e7 v c o a9 tim_8 6 1 g 3 p c lk b4 io_vdd g 1 din18 a2 din19 b3 lf a7 c p_vdd a10 c p_ g nd b10 din17 a1 c ore_vdd k8 r s v h 6 dete c t_tr s f3 c ore_ g nd e 6 v c o_ g nd b9 din1 6 b2 c ore_vdd g 10 pd_vdd a 6 pd_vdd b 6 c ore_ g nd d5 s tandby d3 r s v k7 r s v j 7 r s v j6 din14 c 2 din15 b1 c ore_ g nd c 5 c ore_ g nd b5 n c d 6 n c d7 dvb_a s i g 5 lo c ked h4 r s v h5 r s v k 6 din12 c 3 din13 c 1 n c d8 n c e8 n c f8 s d/hd e3 c ore_ g nd e5 c ore_vdd e1 r s v k5 io_vdd h10 din10 d2 din11 d1 c ore_ g nd f4 c ore_ g nd j 8 c ore_ g nd g 9 20bit/10bit g 4 c ore_ g nd f5 c ore_vdd a5 r s v j 5 io_ g nd g 2 din8 f2 din9 f1 c ore_ g nd f7 c d_ g nd f9 c d_ g nd e9 iopro c _en/di s g 7 s mpte_bypa ss g6 re s et g 8 r s v j 4 an c _blank h3 din 6 h2 din7 h1 c d_ g nd d9 c ore_ g nd e2 r s v h7 cs _tm s k9 sc lk_t c k j 10 s dout_tdo j 9 r s v k4 h/h s yn c a4 din4 j 2 din5 j 1 c ore_ g nd f 6 pd_ g nd c 8 pd_ g nd c 7 pd_ g nd c6 s do_en/di s d4 s din_tdi k10 v/v s yn c c 4 io_ g nd h9 din2 k2 din3 k1 r s et f10 c d_vdd e10 s do c 10 s do d10 c d_ g nd c 9 j ta g /ho s t h8 f/de a3 n c e4 din0 k3 din1 j 3 u18 gs 1572 u18 gs 1572 c 88 10nf c 88 10nf (np) c 7 6 (np) r 6 9 (np) r 6 9 (np) r55 0r r55 0r c6 5 10nf r 6 7 (np) r 6 7 (np) r54 0r r54 0r c 79 10nf c 79 10nf c 78 (np) c 78 (np) c 84 10nf c 84 10nf c 89 10nf c 89 10nf c 82 10nf c 82 10nf r58 10k r58 10k v c tr 5 g nd 4 g nd 8 g nd 2 v cc 7 o/p 1 n c 3 g nd 6 u15 g o1555 u15 g o1555 * r& c refer to s e c tion 4.10.2 for loop filter c omponent values.
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 60 of 64 6. references & relevant standards smpte 125m component video signal 4:2:2 C bit parallel interface smpte 259m 10-bit 4:2:2 component and 4fsc composite digital signals - serial digital interface smpte 260m 1125 / 60 high definition production system C digital representation and bit parallel interface smpte 267m bit parallel digital interface C component video signal 4:2:2 16 x 9 aspect ratio smpte 274m 1920 x 1080 scanning analog and parallel digital interfaces for multiple picture rates smpte 291m ancillary data packet and space formatting smpte 292m bit-serial digital interface for high-definition television systems smpte 293m 720 x 483 active line at 59.94 hz progressive scan production C digital representation smpte 296m 1280 x 720 scanning, analog and digital representation and analog interface smpte 352m video payload identification for digital television interfaces smpte rp165 error detection checkwords and status flags for use in bit-serial digital interfaces for television smpte rp168 definition of vertical interval switching point for synchronous video switching
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 61 of 64 7. package & ordering information 7.1 package dimensions
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 62 of 64 7.2 solder reflow profiles the GS1572 is available in a pb-free packag e. it is recommende d that the pb-free package be soldered with pb-free paste using the reflow profile shown in figure 7-1 . figure 7-1: maximum pb-free solder reflow profile 7.3 marking diagram 25 c 150 c 200 c 217 c 2 6 0 c 250 c time temperature 8 min. max 6 0-180 se c . max 6 0-150 se c . 20-40 se c . 3 c /se c max 6 c /se c max pin 1 id GS1572 xxxxe3 yyww yyww - date code yy - 2-digit year ww - 2-digit week number xxxx - l ot/work order id
GS1572 multi-rate serializer with cable driver and clockcleaner tm data sheet 44262 - 4 march 2009 63 of 64 7.4 packaging data 7.5 ordering information parameter value package type 11mm x 11mm 100-ball lbga package drawing reference jedec m0192 (with exceptions noted in package dimensions on page 61 ). moisture sensitivity level 3 junction to case thermal resistance, j-c 15.4c/w junction to air thermal resistance, j-a (at zero airflow) 37.1c/w junction to board thermal resistance, j-b 26.4c/w psi, 0.4c/w pb-free and rohs compliant yes part number package pb-free temperature range GS1572-ibe3 100-ball bga yes -20c to 85c
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